SR flip-flop is one of the fundamental sequential circuit possible. This simple flip flop is basically a one-bit memory storage device that has two inputs, one which will ‘Set’ the device (i.e. the output is 1), and is labelled S and other which will Reset the device (i.e. the output is 0), labelled R. The name SR stands for “Set-Reset“. The logic symbol for SR flip flop is shown in fig.1.
Likewise SR latch, SR flip-flop can be constructed by using cross-coupled NAND and NOR gates. Since flip-flops are controlled by clock transitions, therefore we will provide a clock to our SR flip flop circuit.
SR NAND flip flop
The circuit diagram of NAND SR flip flop is shown in fig.2.
Working of SR Nand flip flop
Now we will understand the working of SR NAND flip flop by taking consideration into the SR NAND latch.
It is clear from the fig.2 that
and
Case 1: Now if CLK is 0 then S*=1 and R*=1 and here S and R will be treated as don’t care conditions, then we get Q and
in memory state i.e. holding previous values.
Case 2: if CLK=1 then S*=
and R*=
, now there will be 4 more cases depending upon the values of S and R.
Case 2(a): S=0 and R= 0 then S* and R* both becomes 1 and we get outputs Q and holding memory state.
Case 2(b): S=0 and R=1 then S*=1 and R*= 0 then we get Q= 0 and =1, we get both outputs as complement of each other.
Case 2(c): S=1 and R=0 then S*=0 and R*=1 them we get Q= 1 and =0.
Case 2(d): S=1 and R=1 then S*=0 and R*=0 then we get Q and in the invalid state i.e. not used condition.
The truth table of SR NAND flip flop is given below.
| CLK | S | R | Q | |
| 0 | × | × | Memory state | |
| 1 | 0 | 0 | Memory state | |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | Invalid | |
Note: × is the don’t care condition.
Characteristics table for SR Nand flip-flop
Characteristics table is determined by the truth table of any circuit, it basically takes Qn, S and R as its inputs and Qn+1 as output. Qn+1 represents the next state while Qn represents the present state.
While dealing with the characteristics table, the clock is high for all cases i.e CLK=1.
The characteristics table for the SR flip flop is given below.
| S | R | Qn | Qn+1 |
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | × |
| 1 | 1 | 1 | × |
Excitation table for SR NAND flip flop
Excitation table is determined by the characteristics table. The inputs are Qn and Qn+1 and outputs are S and R. The excitation table for SR flip flop is given below.
| Qn | Qn+1 | S | R |
| 0 | 0 | 0 | × |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | × | 0 |
SR NOR flip flop
The circuit diagram of the SR NOR flip flop is shown in fig.3.
Working of SR NOR flip flop
Similar to SR NAND flip flop we will going to understand the SR NOR flip flop taking SR NOR latch into consideration.
It is clear from fig.3 that
and
Case 1: When CLK = 0 then S*=0 and R*=0 which means the outputs are now holding the previous sates i.e. flip flop is in memory state independent of the values of S and R.
Case 2: When CLK=1 then R*= R and S*=S, now there will be 4 more cases depending upon the values of S and R.
Case 2(a): S= 0 and R= 0 then S*=0 and R*=0 then we get Q and again in memory state.
Case 2(b): S= 0 and R= 1 then S*=0 and R*= 1 then we get Q= 0 and = 1.
Case 2(c): S= 1 and R= 0 then S*= 1 and R*= 0 then we get Q=1 and = 0.
Case 2(d): S= 1 and R= 1 then S*= 1 and R*= 1 then we get the invalid state which should not be used.
The Truth table of SR NOR flip-flop is given below.
| CLK | S | R | Q | |
| 0 | × | × | Memory state | |
| 1 | 0 | 0 | Memory state | |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | Invalid state | |
Since we can clearly see that truth tables for both the SR NAND and NOR flip flops are same, so we will get the same characteristics and excitation table for both the flip flops.
Author:
Shivani Gupta
Institute of Engineering and Technology
Lucknow, U.P.
it was informative to me
In the characteristics table, for inputs S=1 and R=1, Qn+1 is invalid as per the truth table. Then why do we treat it as a “don’t care”? Are invalid state and “Don’t care” the same thing?
dont care and invalid are not the same thing but in characterstic table the value of S=1 and R=1 but Qn is 0 in 1st condition and 1 in second which means the output is not determined if its either 0 or 1 so its dont care