A Latch is a basic memory element that operates with signal levels (rather than signal transitions) and stores 1 bit of data. Latches are said to be level sensitive devices. Latches are useful for storing information and for the design of asynchronous sequential circuits.
SR latch using NOR gates
The SR latch constructed using two cross-coupled NOR gates is shown in Fig.1. The latch has two useful states. When output Q=1 and Q’= 0, the latch is said to be in the Set state. When Q= 0 and Q’=1, it is in Reset state. Normally, outputs Q and Q’ are complement to each other.
Working of SR NOR latch
Case 1: When S=0 and R=1, then by using the property of NOR gate (if one of the inputs to the gate is 1 then the output is 0), therefore the output Q=0 since R=1 and if Q=0 and S=0 then Q’ becomes 1, hence Q and Q’ are complement to each other. This is the Reset condition as output Q=0 when R=1.
Now if R goes back to 0, the circuit remains in the Reset state i.e in another word if we remove the inputs i.e. S=0 and R= 0, then let if Q’ =1 then again by using the property of NOR gate Q becomes 0, it seems we get the previous output which gets stored in the latch, therefore S=0 and R=0 are called as memory condition.
Case 2: When S=1 and R=0, then by using the property of NOR gate, we get Q’ =0 and now if R=0 and Q’ =0 then Q becomes 1 which is the condition for the Set state. Similarly, if S goes back to 0, then the circuit will remain in the set state, i.e. S=0 and R=0 is the memory or hold state which means latch is holding or storing the previous output.
Case 3: When S=1 and R= 1, then both the outputs Q and Q’ becomes 0 by using the property of NOR gate, which violates the requirement that both the outputs must be complement of each other. In normal operation, this condition is avoided by making sure that 1’s are not applied to both the inputs simultaneously.
The truth table of SR NOR latch is given below
|1||1||Invalid state (not used)|
SR latch using NAND gates
The SR latch using two cross-coupled NAND gates is shown in Fig.2.
Working of SR NAND latch
Case 1: When S=0 and R=1 then by using the property of NAND gate (if one of the inputs to the gate is 0 then the output is 1), therefore Q becomes 1 as S=0, putting the latch in the Set state and now since Q= 1 and R=1 then Q’ becomes 0, hence Q and Q’ are complement to each other. Now when the S input goes back to 1, the circuit remains in the set state, which means when S=1 and R= 1, the latch is in memory state i.e. holding the previous output.
Case 2: When S=1 and R=0 then Q’ becomes 1 and since Q’=1 and S=1 then Q goes to 0, putting the latch in the Reset state and both the outputs Q and Q’ are complement to each other. Similarly, when the R input goes back to 1, the circuit remains in the reset state, which simply means when S=1 and R=1 the latch is in-memory state.
Case 3: When both the inputs S and R are 0 then by using the property of NAND gate we get both the outputs Q and Q’ equals to 1, which violates our assumption of complementary outputs, hence this condition is not used when operating with NAND SR latch.
The truth table of SR NAND latch is given below
|0||0||Invalid condition (not used)|
|1||1||Memory/ hold state|
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