Latches, Flip-Flops, and Timers MCQs

16. Consider the following statements

1. Race-around condition occurs in a JK flip-flop when the inputs are 1, 1.
2. A flip-flop is used to store one bit of information.
3. A transparent latch consists of D-type flip-flops.
4. Master-slave configuration is used in a flip-flop to store 2-bits of information.

Which of the above statements are correct?

  1. 1, 2 and 3 only
  2. 1, 2 and 4 only
  3. 1, 2, 3 and 4
  4. 3 and 4 only

Answer. a

17. An R-S latch is

  1. combinational circuit
  2. synchronous sequential circuit
  3. one-bit memory element
  4. one clock delay element

Answer. c

18. A master-slave flip-flop has the characteristic that

  1. change in the input immediately reflected in the output.
  2. change in the output occurs when the state of the master is affected.
  3. change in the output occurs when the state of the slave is affected.
  4. both the master and the slave states are affected at the same time.

Answer. c

19. For a J-K flip-flop, its J input is tied to its own \overline{Q} output and its K input is connected to its own Q output. If the flip-flop is fed with a clock of frequency 1 MHz. Its Q output frequency will be in _______ MHz.

  1. 0.5
  2. 0.25
  3. 0.75
  4. 0.6

Answer. a

20. The present output Qn of an edge triggered J-K flip-flop is logic 0. If J = 1, then Qn+1

  1. cannot be determined
  2. will be logic 0
  3. will be logic 1
  4. will race around

Answer. c

21. Which of the following flip-flop is used as a latch?

  1. JK flip-flop
  2. RS flip-flop
  3. T flip-flop
  4. D flip-flop

Answer. b

22. When a flip-flop is reset, its output will be

  1. Q=0;\overline{Q}=1
  2. Q=1;\overline{Q}=0
  3. Q=0;\overline{Q}=0
  4. Q=1;\overline{Q}=1

Answer. a

23. In the toggle mode, a JK flip-flop has

  1. J=0;K=1
  2. J=1;K=0
  3. J=0;K=0
  4. J=1;K=1

Answer. d

24. The output Qn of JK flip-flop is zero. It changes to 1 when a clock pulse is applied. The input Jn and Kn are respectively

  1. 1 and x
  2. 0 and x
  3. x and 0
  4. x and 1

Answer. a

25. In a JK flip-flop, J is connected to $\overline{Q} and K is connected to Q outputs. The JK flip-flop converts into a

  1. RS flip-flop
  2. D flip-flop
  3. T flip-flop
  4. Clocked RS flip-flop

Answer. c

26. The race around condition occurs when

  1. J = 0, K = 0
  2. J = 0, K = 1
  3. J = 1, K = 0
  4. J = 1, K = 1

Answer. d

27. If tp is pulse width, Δt is the propagation delay, T is period of pulse train then the following condition can avoid the race around condition.

  1. tp = Δt = T
  2. 2tp > Δt > T
  3. 2tp < Δt > T
  4. 2tp < Δt < T

Answer. d

28. D flip-flop can be configured from a 

  1. JK flip-flop and an inverter
  2. RS flip-flop
  3. RS flip-flop and an inverter
  4. both (a) and (b)

Answer. a

29. How many flip-flops are in the 7475 IC?

  1. 7
  2. 6
  3. 4
  4. 1

Answer. c

30. Propagation delay time, tPLH, is measured from the ________.

  1. clear input to the HIGH-to-LOW transition of the output
  2. preset input to the LOW-to-HIGH transition of the output
  3. triggering edge of the clock pulse to the HIGH-to-LOW transition of the output
  4. triggering edge of the clock pulse to the LOW-to-HIGH transition of the output

Answer. d

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