Logic Gates MCQs

1. When the input to an inverter is LOW (0), the output is

(a) HIGH or 0

(b) LOW or 0

(c) HIGH or 1

(d) LOW or 1

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Answer. c

2. An inverter performs an operation known as

(a) complementation

(b) assertion

(c) inversion

(d) both answers (a) and (c)

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Answer. d

3. The output of an AND gate with inputs A, B and C is 0 (LOW) when

(a) A = 0, B = 0, C = 0

(b) A = 0, B = 1, C = 1

(c) both answers (a) and (b)

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Answer. c

4. The output of an OR gate with inputs A, B and C is 0 (LOW) when

(a) A = 0, B = 0, C = 0

(b) A = 0, B = 1, C = 1

(c) both answers (a) and (b)

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Answer. a

5. A pulse is applied to each input of a 2-input NAND gate. One pulse goes HIGH at t = 0 and goes back LOW at t = 1 ms. The other pulse goes HIGH at t = 0.8 ms and goes back LOW at t = 3 ms. The output pulse can be described as follows:

(a) It goes LOW at t = 0 and back HIGH at t = 3 ms.
(b) It goes LOW at t = 0.8 ms and back HIGH at t = 3 ms.
(c) It goes LOW at t = 0.8 ms and back HIGH at t = 1 ms.
(d) It goes LOW at t = 0.8 ms and back LOW at t = 1 ms.

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Answer. c

6. A pulse is applied to each input of a 2-input NOR gate. One pulse goes HIGH at t = 0 and goes back LOW at t = 1 ms. The other pulse goes HIGH at t = 0.8 ms and goes back LOW at t = 3 ms. The output pulse can be described as follows:

(a) It goes LOW at t = 0 and back HIGH at t = 3 ms.
(b) It goes LOW at t = 0.8 ms and back HIGH at t = 3 ms.
(c) It goes LOW at t = 0.8 ms and back HIGH at t = 1 ms.
(d) It goes HIGH at t = 0.8 ms and back LOW at t = 1 ms.

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Answer. a

7. A pulse is applied to each input of an exclusive-OR gate. One pulse goes HIGH at t = 0 and goes back LOW at t = 1 ms. The other pulse goes HIGH at t = 0.8 ms and goes back LOW at t = 3 ms. The output pulse can be described as follows:

(a) It goes HIGH at t = 0 and back LOW at t = 3 ms.
(b) It goes HIGH at t = 0 and back LOW at t = 0.8 ms.
(c) It goes HIGH at t = 1 ms and back LOW at t = 3 ms.
(d) both answers (b) and (c)

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Answer. d

8. A positive-going pulse is applied to an inverter. The time interval from the leading edge of the input to the leading edge of the output is 7 ns. This parameter is

(a) speed-power product

(b) propagation delay, tPHL

(c) propagation delay, tPLH

(d) pulse width

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Answer. b

9. Most PLDs utilize an array of

(a) NOT gates
(b) NOR gates
(c) OR gates
(d) AND gates

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Answer. d

10. The rows and columns of the interconnection matrix in an SPLD are connected using

(a) fuses

(b) switches

(c) gates

(d) transistors

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Answer. a