Latches, Flip-Flops, and Timers MCQs

1. An active HIGH input S-R latch is formed by the cross-coupling of

1. two NOR gates
2. two NAND gates
3. two OR gates
4. two AND gates

3. For what combinations of the inputs D and EN will a D latch reset?

1. D = LOW, EN = LOW
2. D = LOW, EN = HIGH
3. D = HIGH, EN = LOW
4. D = HIGH, EN = HIGH

4. A flip-flop changes its state during the

1. complete operational cycle
2. falling edge of the clock pulse
3. rising edge of the clock pulse
4. both answers (b) and (c)

5. The purpose of the clock input to a flip-flop is to

1. clear the device
2. set the device
3. always cause the output to change states
4. cause the output to assume a state-dependent on the controlling (J-K or D) inputs.

6. For an edge-triggered D flip-flop,

1. a change in the state of the flip-flop can occur only at a clock pulse edge
2. the state that the flip-flop goes to depends on the D input
3. the output follows the input at each clock pulse
4. all of these answers

7. A feature that distinguishes the J-K flip-flop from the D flip-flop is the

1. toggle condition
2. preset input
3. type of clock
4. clear input

8. A flip-flop is SET when

1. J = 0, K = 0
2. J = 0, K = 1
3. J = 1, K = 0
4. J = 1, K = 1

9. A J-K flip-flop with J = 1 and K = 1 has a 10 kHz clock input. The Q output is

1. constantly HIGH
2. constantly LOW
3. a 10 kHz square wave
4. a 5 kHz square wave

10. D flip-flop can be made from a J-K flip flop by making

1. J = K
2. J = K = 1
3. J = 0, K = 1
4. $J =\overline{K}$

11. For a J-K flip-flop, Q_n is output at time step t_n. Which of the following boolean expressions represents Q_n+1?

1. $J_n\overline{Q}_n+\overline{K}_nQ_n$
2. $J_nQ_n+K_n\overline{Q}_n$
3. $\overline{J}_nQ_n+K_n\overline{Q}_n$
4. $J_nQ_n+\overline{K}_n\overline{Q}_n$

12. A J-K flip-flop can be made from an S-R flip-flop by using two additional

1. AND gate
2. OR gate
3. NOT gate
4. NOR gate

13. Which of the following is correct for a gated D-type flip flop?

1. the output is either SET OR RESET as soon as the D input goes HIGH or LOW
2. the output complement follows the input when enabled
3. only one of the inputs can be HIGH at a time
4. the output toggles if one of the inputs is held HIGH

14. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?

1. Asynchronous operation
2. low input voltage
3. gate impedance
4. cross coupling

15. Race-around condition occurs in

1. multiplexer
2. ROM
3. flip-flops
4. voltage regulators