4-Channel Electronic Sampling System

In this article, we will discuss the working of a 4-Channel Electronic Sampling System. The basic circuit diagram is shown in figure1. Analog inputs are channels 1, 2,3, and 4. The PMOS transistor acts as a switch here. It is in ON state when the gate input is 0 (or low).

Fig1. 4-Channel Electronic Sampling System

The following table gives the flip-flop conditions for the channel selector.

QA QB Channel selected  
1 (high) 1 (high) 1
0 (low) 1 (high) 2
1 (high) 0 (low) 3
0 (low) 0 (low) 4


1st clock pulse:

QA = 1

G goes from 1 to 0

QB = 0, QA = 1,  = 1

Gate 3 will open.

2nd clock pulse:

QA = 0

G goes from 0 to 1

QB = 1, = 1

Gate 2 will open.

3rd clock pulse:

QA = 1

G goes from 1 to 0

QB = 1,  = 0

Gate 1 will open.

4th clock pulse:

QA = 0

G goes from 0 to 1

QB = 0, = 1

Gate 4 will open.

When inputs through a NAND gate are high corresponding transistor act as low resistance path and corresponding channel is allowed to pass till the next clock pulse comes. The duration of clock pulses can be adjusted through a monostable multivibrator with pulse width adjusting control.

Output QA toggles only when its input goes from 0 to 1 i.e. for every clock pulse.

Output QB toggles only when Qgoes from 1 to 0 i.e. when G goes from 0 to 1.

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