Hardware Interrupts in 8085 Microprocessor

An interrupt is a signal to the processor, generated by hardware or software indicating an immediate attention needed by an event. In this article, we will learn about hardware interrupts.

In 8085 microprocessor, there is 5 hardware interrupts.

S.No. Name of Interrupt Priority Vector address Masking type Types of trigger
1 TRAP Highest (1) 0024 H Non-maskable Edge & Level
2 RST 7.5 2 003C H Maskable Edge
3 RST 6.5 3 0034 H Maskable Level
4 RST 5.5 4 002C H Maskable Level
5 INTR Least (5) Non-vectored interrupt Maskable Level

Note:

1. TRAP is a Non-maskable interrupt.

2. TRAP is also known as RST 4.5

On the basis of different characteristics, interrupts are classified into different groups.

  1. Maskable & Non-maskable interrupts
  2. Vectored & Non-Vectored interrupt

Maskable & Non-maskable interrupts

Mask means to block. An interrupt that can be turned off or disabled or ignored by the programmer or another interrupt is called as a maskable interrupt. The interrupts that come from the peripheral devices are the maskable interrupt. For example mouseclick, memory read, etc.

An interrupt that can not be turned off or disabled or ignored by the programmer or another interrupt is called as a non-maskable interrupt.

Note: To control interrupt process in 8085, a interrupt enable flip-flop is present.

  • If interrupt enable flip-flop is SET ⇒ Interrupt process enable
  • If interrupt enable flip-flop is RESET ⇒ Interrupt process disable

Note: Masking & non-masking concept is valid only when interrupt process is enabled.

To SET or RESET interrupt enable flip-flop, two instructions are defined.

1. EI

  • Instruction word size  ⇒ 1 Byte
  • interrupt enable flip-flop will get SET.
  • An interrupt process will enable.
  • Addressing mode ⇒ Implicit addressing mode

2. DI

  • Instruction word size  ⇒ 1 Byte
  • interrupt enable flip-flop will get RESET.
  • An interrupt process will disable.
  • Addressing mode ⇒ Implicit addressing mode

Note:

1. EI & DI instructions are the machine control instructions. So the status of flag will not affect.

2. TRAP is independent of EI & DI.

Vectored & Non-Vectored interrupt

When vectored interrupt acknowledge control execution will jump at fixed vector location of memory. TRAP, RST 7.5, RST 6.5, RST 5.5 are vectored interrupts.

Vector location to a non-vectored interrupt provided externally. INTR is a non-vectored interrupt.

Interrupts Priority

TRAP

RST 7.5

RST 6.5

RST 5.5

INTR

Top to bottom priority decreases. i.e. TRAP has the highest priority while INTR has the lowest priority.

Note: When an interrupt is acknowledged following steps execute automatically.

  1. Execution of the current instruction will complete first.
  2. Address of next instruction will store at the top of the stack.
  3. DI instruction will execute automatically.
  4. Execution will transfer to interrupt subroutine.

Note:

1. A programmer should write EI instruction at the last of interrupt service routine.

2. In externally initiated signal HOLD has the highest priority.

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